The present invention relates to a method of, and frame synchronizing device for, synchronizing systems having a digital interface in audio/video (A/V) apparatuses.
As almost all A/V apparatuses becomes digitized, one apparatus can be controlled by another using a digital interface. When moving picture data is received, the picture cannot be properly restored unless the apparatuses having the digital interface are synchronized. A device that performs this task is referred to as a frame synchronizing device.
FIG. 1 is a block diagram of a conventional frame synchronizing device. A digital interface (DIF) 110 synchronizes external equipment (a master system) which transfers the transport packet, with a digital recording and reproducing apparatus (a slave system), using a cycle timer 113, a time stamp extractor 114 and a comparator 115. The digital interface 110 extracts a time stamp from a transport packet received during a digital interface mode, operates a PLL circuit 120 according to a frame pulse (frame_dif) extracted from frame starting time information in the time stamp, divides a clock signal generated in the PLL circuit 120 by using a divider 130, applies a frame reset pulse (frp) synchronized with the divided clock signal to a channel encoder 140 and a source decoder 150, and applies a horizontal synchronizing signal (H_sync) synchronized with the divided clock signal and a field signal (field) to a video encoder 160. The digital recording and reproducing apparatus, which has an inner bus margin, represents digital video cassette recorder and all digital video camera (DVC) systems such as digital camcorders. The digital recording and reproducing apparatus includes a recording system, constructed of a source encoder (not shown), and a channel encoder 140. It also includes a reproducing system, constructed of a channel decoder (not shown), a source decoder 150 and a video encoder 160. The PLL circuit 120 shown in FIG. 1 also includes a phase discriminator (PD) 121, a low pass filter (LPF) 122 and a voltage controlled crystal oscillator (VCXO) 123.
When a synchronizing signal is required for a system, for example, the channel encoder 140, the source decoder 150, and the video encoder 160, it is generated in the divider 130. Then data is read from a FIFO memory 112 and transferred to the channel encoder 140 and the source decoder 150 through an AV_bus. The data is read according to a control signal (CON), generated during fixed timing on the basis of the frame reset pulse (frp), which is generated in the divider 130. At this time, a color burst signal is generated by being frame-locked inside the video encoder 160 for receiving as input the horizontal synchronizing signal (H_sync) and the field signal (field). The system maintains a four field sequence or an eight field sequence. When receiving color and mono broadcasts in an NTSC broadcasting system, picture quality of the color burst signal deteriorates unless the four field sequence is maintained, because the phase is identical every four fields because a phase difference of 180xc2x0 exists between lines. In the color burst signal of a PAL broadcasting system, an eight field sequence should be maintained, because the phase is identical every eight fields because a phase difference of 270xc2x0 exists between lines.
FIG. 2 is a detailed block diagram of the divider 130 shown in FIG. 1. The divider 130 includes:
a) a first line counter 131 for receiving a frequency signal of 18 MHz from the PLL circuit 120 and counting lines;
b) a first pixel counter 132 for counting pixels;
c) a system frame reset pulse generator 133 for receiving the outputs of the first line counter and the first pixel counter and generating the frame reset pulse (frp);
d) a second line counter 134 for receiving a frequency signal of 13.5 MHz from the PLL circuit 120 and counting lines;
e) a second pixel counter 135 for counting pixels; and
f) a video encoder synchronism generator 136 for receiving the outputs of the second line counter and the second pixel counter and generating a horizontal synchronizing signal (H-sync) and a field signal (field).
During a digital interface mode, the PLL circuit 120 locks a clock signal oscillating at 54 MHz to a frame pulse (frame_dif) of 15 Hz generated in the digital interface 110, and provides the clock signal to the divider 130 as system clock. The divider 130 divides the system clock and generates a synchronizing signal required for the channel encoder 140, the source decoder 150, and the video encoder 160. When a synchronizing signal, synchronized with the frame pulse of a master system, is generated from a slave system during the digital interface mode, the data stored in the digital interface 110, which is transferred from the master system, is read and transferred to the slave system.
However, the performance of the above-mentioned frame synchronizing device deteriorates because the clock signal generated in the PLL circuit 120 cannot be used unless an extremely precise voltage controlled oscillator is designed. This is because a 54 MHz clock is locked using the frame pulse (frame_dif) input with a frequency of only 15 Hz. Therefore, in a conventional frame synchronizing device, high-priced components, such as a voltage controlled crystal oscillator, must be used because the PLL is locked by a low frame frequency.
It is an object of the present invention to provide a frame synchronizing device for synchronizing systems, by generating a frame reset signal based on frame time information of external equipment output through a digital interface, and resetting the entire system according to the frame reset signal.
It is another object of the present invention to provide in a recording and reproducing apparatus having a digital interface, a frame synchronizing device for synchronizing systems, by free-oscillating a color signal during a digital interface mode in order to accommodate a frame reset signal having a variable period, when a system is reset by the frame reset signal generated based on external frame time information.
It is still another object of the present invention to provide a frame synchronizing method for synchronizing systems, by generating a frame reset signal based on frame time information of external equipment output through a digital interface, and resetting the entire system by the frame reset signal.
It is still further another object of the present invention to provide a frame synchronizing method for synchronizing systems, by free-oscillating a color signal during a digital interface mode in order to accommodate a frame reset signal having a variable period, when a system is reset by the frame reset signal generated based on external frame time information.
To achieve the above objects, a frame synchronizing device for synchronizing systems is provided which has a digital interface for extracting frame time information included in a received signal from an external source, and a generator for generating a frame reset signal based on the frame time information and synchronizing signals required by the systems, wherein the system is reset by the frame reset signal. The frame synchronizing device according to the present invention further comprises a signal processor for free-oscillating a color burst signal during a digital interface mode when the received signal is source-decoded and then encoded into a display signal and for resetting the color burst signal according to the synchronizing signals during a normal mode.
A frame synchronizing method for synchronizing systems having a digital interface comprises the steps of extracting frame time information included in a received signal from an external source during a digital interface mode and generating a frame reset signal based on the frame time information and synchronizing signals required by the systems and resetting the systems by the frame reset signal.
Also, the frame synchronizing method according to the present invention further comprises the steps of free-oscillating a color burst signal during a digital interface mode and resetting the color burst signal at a period of a predetermined number of fields according to the horizontal synchronizing signal and the field signal during a normal mode.